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AT86RF232
11 AT86RF232 Extended Feature Set
11.1 Security Module (AES)
The security module (AES) is characterized by:
? Hardware accelerated encryption and decryption
? Compatible with AES-128 standard (128-bit key and data block size)
? ECB (encryption/decryption) mode and CBC (encryption) mode support
? Stand-alone operation, independent of other blocks
11.1.1 Overview
The security module is based on an AES-128 core according to FIPS197 standard,
refer to [5]. The security module works independent of other building blocks of the
Atmel AT86RF232, encryption and decryption can be performed in parallel to a frame
transmission or reception.
Controlling the security block is implemented as an SRAM access to address space
0x82 to 0x94. A Fast SRAM access mode allows simultaneously writing new data and
reading data from previously processed data within the same SPI transfer. This access
procedure is used to reduce the turnaround time for ECB and CBC modes, see
Section 11.1.5 .
In addition, the security module contains another 128-bit register to store the initial key
used for security operations. This initial key is not modified by the security module.
11.1.2 Security Module Preparation
The use of the security module requires a configuration of the security engine before
starting a security operation. The following steps are required:
Table 11-1. AES Engine Configuration Steps.
Step
1
2
3
4
5
Description
Key Setup
AES mode
Write Data
Start operation
Read Data
Description
Write encryption or decryption key to SRAM
Select AES mode: ECB or CBC
Select encryption or decryption
Write plaintext or cipher text to SRAM
Start AES operation
Read cipher text or plaintext from SRAM
Section
11.1.3
11.1.4.1
11.1.4.2
11.1.5
11.1.5
Before starting any security operation a key must be written to the security engine, refer
to Section 11.1.3 . The key set up requires the configuration of the AES engine KEY
mode using register bits AES_MODE (SRAM address 0x83, AES_CTRL).
The following step selects the AES mode, either electronic code book (ECB) or cipher
block chaining (CBC). These modes are explained more in detail in Section 11.1.4 .
Further, encryption or decryption must be selected with register bit AES_DIR (SRAM
address 0x83, AES_CTRL).
As next the 128-bit plain text or ciphertext data has to be provided to the AES hardware
engine. The data uses the SRAM address range 0x84 – 0x93.
125
8321A – MCU Wireless – 10/11
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